DDC-I’s Deos Safety-Critical RTOS Available for North Atlantic Industries’ 68PPC2 Multicore Open VPX Single Board Computer
DDC-I, a leading supplier of software and professional services for mission- and safety-critical applications, and North Atlantic Industries, a leading provider of embedded systems for mil/aero applications, announced the availability of DDC-I’s Deos safety-critical real-time operating system for NAI’s 68PPC2 T2080 PowerPC OpenVPX single-board computer. The integrated platform comes with complete DO-178C/ED-12C DAL A verification evidence for the Board Support Package, including all network and I/O drivers, greatly accelerating the development, deployment and certification of high-performance safety-critical applications for avionics systems.
DDC-I’s approach to building safety critical software mirrors North Atlantic’s approach to configuring boards, with an emphasis on modular, scalable portable DAL-A verification. Deos utilizes a DAL A linking loader that allows OS binary components and their artifacts to travel separately. NAI’s Configurable Open Systems Architecture (COSA) utilizes highly modular, portable components that can be added or removed, and reapplied to other system configurations with maximum reuse of DAL-A artifacts. This shared commitment to modularity, portability and reuse enables avionics designers utilizing Deos and the COSA architecture to reconfigure their I/O systems with minimal impact on hardware, software and DO-178 recertification.
The 68PPC2 is a 3U OpenVPX NXP T2080 PowerPC single-board computer that can be configured with up to two NAI smart I/O and communications function modules. Featuring an NXP QorlQ T2080 Quad Core e6500 Processor running at 1.5 GHz, and consuming less then 25W, the 68PPC2 is ideally suited for rugged Mil-Aero applications that accelerate deployment of SWaP-optimized systems in air, land and sea applications. The 68PPC2 comes equipped with eight Mbytes of DDR3 SDRAM and 32 Gbytes of SATA II NAND Flash. It also features PCIe, USB, I2C, TTL, and RS-232 interfaces, as well as an optional SATA II for external access to up to 512 Gbytes of expansion memory.
“Advanced SafeMC multicore technology, together with reusable verification evidence, make Deos an ideal environment for developing, hosting, and certifying high-performance safety-critical avionics applications targeting the 68PPC2 and COSA architecture,” said Greg Rose, vice president of marketing and product management at DDC-I. “Deos SafeMC technology uniquely resolves the CAST-32A multicore objectives, enabling it to deliver unmatched performance and determinism for safety-critical applications running on NXP PowerPC multicore processors.”
“We are pleased to be working with DDC-I to offer our joint customers an integrated platform that combines our high-performance multicore capability with a best-in-class safety-critical RTOS,” added Lino Massafra, vice president of sales and marketing at NAI. “Developers requiring the highest level of design assurance now have a rugged, flexible, off-the-shelf solution combining high-performance multicore computing and configurable I/O in a compact, low-power package that accelerates deployment of safety-critical systems.”
Deos is a safety-critical embedded RTOS that employs patented cache partitioning, memory pools, and safe scheduling to deliver higher CPU utilization than any other certifiable safety-critical COTS RTOS on multi-core processors. First certified to DO-178 DAL A in 1998, Deos combines FACE conformance with DO-178C DAL A artifacts, providing a FACE Safety Base Profile that features hard real-time response, time and space partitioning, and both ARINC-653 and POSIX interfaces.
SafeMC technology extends Deos’ advanced capabilities to multiple cores, enabling developers of safety-critical systems to achieve best in class multi-core performance without compromising safety-critical task response and guaranteed execution time. SafeMC employs a bound multiprocessing (BMP) extension of the symmetric multiprocessing architecture (SMP), safe scheduling, and cache partitioning to minimize cross-core contention and interference patterns that affect the performance, safety criticality and certifiability of multi-core systems. These features enable avionics systems developers to address issues that could impact the safety, performance and integrity of a software airborne system executing on Multi-Core Processors (MCP), as specified by the Certification Authorities Software Team (CAST) in its Position Paper CAST-32A for Multi-core Processors.
