DDC-I and Intel Bring Safety-Critical Multi-Core Computing to Avionics Displays and High Compute Sensors
DDC-I, a leading supplier of software and professional services for mission- and safety-critical applications, announced it has teamed with Intel to port its Deos DO-178C safety-critical real-time operating system and Eclipse-based development tools to Intel’s 11th Generation Intel Core i7 multi-core application processor. Intel Core i7 processors running Deos provide a platform for a number of applications, including displays and high compute smart sensors.
Deos has supported the x86 processor architecture with DAL-A artifacts since 1998, with thousands of x86-based Deos systems certified and flying today. With Intel Core i7 processors, Deos extends its existing support for the Intel Atom, Intel Xeon, and other i7 architectures, providing a common certification package (at the binary level) and development tools across all these processors, including our DO-330 qualified tools.
The Intel Core i7 SoC application processor is the 11th generation of Intel Core architecture. Combining 4 CPU cores operating at up to 4.4 GHz with an Intel Iris Xe graphics processor and up to 12 Mbytes of cache, Intel Core i7 features Enhanced Media (AV1 Codec/12b support via 2 VDBOX) and AI/DL Instruction Sets with VNNI support for CV/AI and OpenVINO. Intel Core i7 also provides four DP/HDMI outputs (four 4K or two 8K resolution display outputs), 4 PCIe Gen4 Lanes (CPU), and 12 HSIO (PCH) channels with support for 802.11ac, PCIe Gen 3, and USB4.
“Intel Core i7’s high-performance multi-core architecture, on-chip graphics, and AI processing, together with the availability of certification data, makes it very attractive to our avionics customers,” said Greg Rose, vice president of marketing and product management at DDC-I. “Our SafeMC multi-core technology leverages many of these capabilities, employing techniques like cache partitioning, memory pools, time-space partitioning and slack scheduling. Together they provide an efficient, robust, and deterministic platform that builds on Intel's technology to maximize performance while providing a certifiable multi-core environment by reducing multi-core interference and worst-case response.”
“Intel Core i7 offers a high degree of functional integration, making it ideal for e-Cockpit advanced displays and high-compute smart sensors,” added Tony Franklin, general manager of Federal and Aerospace group at Intel. “DDC-I has been a long-time supporter of the x86 architecture, and we are pleased to be working with them again to offer our joint avionics customers a world-class multi-core safety-critical RTOS platform for our 11th Generation Intel Core i7processors.”
Deos is a safety-critical embedded RTOS that employs patented cache partitioning, memory pools, and safe scheduling to deliver a certifiable system with higher CPU utilization than any other certifiable safety-critical COTS RTOS on multi-core processors. First certified to DO-178 DAL A in 1998, Deos provides a FACE Conformant Safety Base Profile that features hard real-time response, time and space partitioning, and both ARINC-653 and POSIX interfaces.
Deos runs on a broad range of processors. With an emphasis on multi-core applications, Deos scales well in the gamut of avionics applications, from highly deterministic deeply embedded FADECs (Full Authority Digital Engine Control) and flight controls to complex high throughput displays and mission computers.
SafeMC technology extends Deos’ advanced capabilities to multiple cores, enabling developers of safety-critical systems to achieve best in class multi-core performance without compromising safety-critical task response and guaranteed execution time. SafeMC employs a bound multiprocessing (BMP) extension of the symmetric multiprocessing architecture (SMP), safe scheduling, and cache partitioning to minimize cross-core contention and interference patterns that affect the performance, safety criticality and certifiability of multi-core systems. These features enable avionics systems developers to address issues that could impact the safety, performance and integrity of a software airborne system executing on Multi-Core Processors (MCP), as specified by the Certification Authorities Software Team (CAST) in its Position Paper CAST-32A for Multi-core Processors.
