DDC-I, a leading supplier of software and professional services for mission- and safety-critical applications, today announced that it will join Aerospace Innovations complimentary multi-core avionics webinar as a guest speaker on Wednesday, February 26 at 10:00 AM EST. Gary Gilliland, Vice President of Marketing at DDC-I, will speak on behalf of DDC-I and focus on Real-Time Operating System (RTOS) techniques for increasing multi-core performance and determinism for safety-critical avionics applications per FAA and EASA A(M)C20-193 multi-core guidelines.
Register and view the complete abstract & register at
https://aerospace-innovations.com/multicore-avionics-webinar/
The complexity introduced by multi-core and multi-system architectures, which often incorporate diverse elements such as Systems on Chip (SoC) and blend Multi-Core Processors (MCP) with Open Systems Architecture, presents significant testing challenges for avionics systems. Understanding the behavior of these systems and establishing thorough testing protocols can be difficult. Traditional testing approaches, tailored for single-core environments, fall short in ensuring the accuracy and performance of multi-core systems. Challenges are compounded by issues like data control coupling, safety-critical timing analysis for multi-core setups, the need for deterministic behavior, and the demand for extensive coverage testing.
The latest guidelines under A(M)C20-193, which have superseded CAST-32A, address these complexities. To effectively test and verify these systems, it’s crucial to have a deep understanding of both the hardware and software components involved. This webinar will look at the latest in multi-core systems and challenges, the impact AI can have on their testing and the future of multi-core in modular avionics displays.
“This webinar is a must see for avionics developers who want to utilize the latest multi-core technology while meeting the worst-case execution requirements defined in the A(M)C20-193 guidelines,” said Gary Gilliland, Vice President of Marketing at DDC-I. “We look forward to highlighting A(M)C20-193 compliant memory configuration and scheduling techniques at the RTOS level that minimize cache thrashing and shared resource conflicts, thereby delivering superior multi-core performance and determinism for safety-critical applications.”
